Program

Sunday, September 14

17:00-20:00   Check-in & Reception (Via Frangipane, 4)

19:00-21:00   Welcome Buffet (“Center Canteen” - Via Frangipane, 2)

Monday, September 15

07:30-08:45   Breakfast (“Center Canteen”)

08:30-08:45   Registration (“Fresco Room” - La Rocca, Via Frangipane, 6)

08:45-09:00   Welcome

09:00-09:30   Evolutionary Policy Optimization, Keshav Pingali (University of Texas, Austin, USA)

09:30-10:00   Inclusive and Efficient Foundation Models, Manish Gupta (Google DeepMind, India)

10:00-10:30   AI-based ModSim for Computer Architectures and Applications, Adolfy Hoisie (Brookhaven National Laboratories, USA)

10:30-11:00   Coffee

11:00-11:30   The Reconfigurable Future of AI Accelerators, Tulika Mitra (National University of Singapore, Singapore)

11:30-12:00   Flow Computing—A New Way to Boost the Performance of CPUs for Parallel Functionalities, Martti Forsell (Flow Computing Oy, Finland)

12:00-12:30   A Hardware Perspective on AI & HPC: Trends, Trade-Offs, and Promising Solutions, Stefania Perri (University of Calabria, Rende, Italy)

12:45-14:00   Lunch (“Center Canteen”)

14:30-15:00   Scientific Workflow Management for Generative Artificial Intelligence and Machine Learning, Ewa Deelman (University of Southern California, USA)

15:00-15:30   Designing for Trust, Transparency, and Efficiency in Scientific Computing: HPC Nondeterminism, Scalable Checkpointing, and AI-Driven Workflows, Michela Taufer (University of Tennessee, Knoxville, USA)

15:30-16:00   Algorithm Design for Emerging Architectures, Franceso Silvestri (University of Padova, Italy)

16:00-16:30   Optimizing Segmented Operations through Matrix Multiplications: Insights from the Ascend AI Accelerator, Anastasios Zouzias (Huawei, Zurich Research Lab, Switzerland)

16:30-17:00   Coffee

17:00-18:30   Discussion Session I: Managing workflows for AI and HPC, Coordinators: E. Deelman, A. Hoisie, M. Taufer

19:30-21:30   Dinner, Enoteca Bistrot Colonna, Via Mainardi 10/12, 47032 Bertinoro (0543 444333).

Tuesday, September 16

07:30-08:45   Breakfast (“Center Canteen”)

09:00-09:30   Architecting the Future: CXL Memory Disaggregation for large scale AI/ML, HPC workloads, Luis Ancajas (Micron, USA)

09:30-10:00   Falcon and Kameleon: A Chiplet-Based Architecture for Scalable CXL Memory Infrastructure and Accelerated Processing Near Memory, Il Park (Primemas, Korea)

10:00-10:30   Coffee

10:30-11:00   Humble Programming, Revisited, Albert-Jan Yzelman (Huawei, Zurich Research Lab, Switzerland)

11:10-12:30   Discussion Session II: Future platforms for HPC and AI, Coordinators: M. Gupta, T. Mitra, A. Yzelman

12:45-14:00   Lunch (“Center Canteen”)

14:30-18:30   Excursion to Comacchio and Pomposa

19:30-22:00   Social Dinner, Ristorante la Campaza, Via Romea Sud, 395, 48124 Ravenna RA (0544 560294).

Wednesday, September 17

07:30-08:45   Breakfast (“Center Canteen”)

09:00-09:30   On-sensor Vision: Computation Opportunities in the Image Sensor, Paul Kelly (Imperial College London, UK)

09:30-10:00   It was the best of times; it was the worst of times, Henry Tufo (University of Colorado, Boulder, USA)

10:00-10:30   RISC-V HPC for Europe: Unique Chance or Dead End?, Carsten Trinitis (Technical University of Munich, Germany)

10:30-11:00   Coffee

11:00-11:30   Architectural Support for Linear Algebra Acceleration: Bridging ISA Extensions and Programming Interfaces, José Moreira (IBM, T. J. Watson Research Lab., NY, USA)

11:30-12:00   Exploring Data Locality in SpGEMM: A Level-Based Implementation of Gustavson’s Algorithm on Multicore CPUs, Dane Lacey (University of Erlangen, Germany)

12:00-12:30   pyGinkgo: High-performance Sparse Linear Algebra Library for Python, Yu-Hsiang Tsai (Technical University of Munich, Germany)

12:30-14:00   Lunch (“Center Canteen”)

14:30-15:00   Enable ML workloads on HPC infrastructure, Mauro Bianco and Stefano Schuppli (Swiss National Supercomputing Centre, ETH, Switzerland)

15:00-15:30   Smart Network Switches for HPC, Josef Weidendorfer (Technical University of Munich, Germany)

15:30-16:00   How many bits do we need? HPC lessons from ML hardware and software, Peter Thoman (University of Innsbruck, Austria)

16:00-16:30   Coffee

16:30-18:00   Discussion Session III: Numerical computing for the AI era, Coordinators: P. Kelly, J. Moreira, A. Zouzias

19:30-21:30   Dinner, Ristorante Pizzeria La Grotta, Viale Roma 37, Bertinoro (0543 444582).

Thursday, September 18

07:30-08:45   Breakfast (“Center Canteen”)

09:00-09:30   Precision-Aware Accumulation: Hardware–Software Co-Design for Block Floating Point Arithmetic, Filip Wojcicki (Imperial College London, UK)

09:30-10:00   Neural Net Guided Branch Prediction Predicting Hard-to-Predict Branches with Minimal Hardware Cost, Luke Panayj (Imperial College London, UK)

10:00-10:30   Techniques in Achieving Better Offset Data Prefetching, Jacky Wong (Imperial College London, UK)

10:30-11:00   Coffee

11:00-11:30   On some Communication Complexity Properties of Linear Transformations, Gianfranco Bilardi (University of Padova, Italy)

11:30-13:00   Discussion Session IV: Efficient Architectures for AI and ML, Coordinators: M. Forsell, F. Silvestri, J. Weidendorfer

Adjourn

13:30-14:30   Lunch (“Center Canteen”)

19:30-21:30   Dinner (“Center Canteen”)